January 4, 2020. Our paper entitled: “A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET” has been accepted for publication in IEEE JSSC. This article reports one of the lowest power high-speed links, that can be employed in applications such as High-Performance Computing and Machine Learning [Link].
August 14, 2019. New open positions are available: LCAS is hiring post-docs and PhD students. If you are interested in design of advanced analog circuit for high-speed communication systems, please do not hesitate sending us your CV [armin DOT tajalli AT utah DOT edu].
February 21, 2019. The latest results of our research on Serial Communications will be presented in ISSCC (Forum 5: 56 Gb/s to 112 Gb/s and Beyond: Design Challenges and Solutions in Wireline Communications). The lecture is entitled: Non-Differential Techniques: Multi-Wire Multi-Level I/O [Link].
April 21, 2019. The works of Senior Project students working with LCAS has been accepted for publication in IEEE NEWCAS’2019 (Munich, Germany) ! The paper is entitled: CMOS Amplifier Design Based on Extended gm/ID Methodology. Congratulations to the team: Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchel Crane, Anthony Baily, and Reuben Morell. The team is proposing a very interesting and practical algorithm to design analog circuits based on an extended gm/Id methodology.
May 12, 2019. The works of Senior Project students working with LCAS has been accepted for publication in IEEE MWCAS’2019 (Dallas, US) ! The paper is entitled: Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. Congratulations to the team: Jacob Atkinson, Amin Aghighi, Stuart Anderson, Mitchel Crane, and Anthony Baily. This article is based on an extension to the earlier work of this group.
May 24, 2019. Our recent research on signaling methods for high-speed chip-to-chip communications has been accepted for publication in IEEE MWCAS’2019 (Dallas, US) ! The paper is entitled: Spectrum Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. Congratulations to the team: Rajath Bindiganavile. This article is based on collaboration with an industrial partner [Link].
May 30, 2019. We are presenting our recent research results in the field of wireline communications in the 2019 North American Workshop on Silicon Photonics for High-Performance Computing – SPHPC (Rocky Mountain, Colorado, US) ! The seminar is entitled: Spectrum Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. A poster will be also presented by Rajath Bindiganavile, entitled: Toward Tb/s/mm Communications Over Copper.
June 11, 2019. A paper entitled: A 1.04-pJ/b 417Gb/s/mm USR Link in 16nm FinFET will be presented in VLSI Symposium, in Kyoto, Japan [Link].