April 4, 2019. Eiger Peak is a team of electrical engineering undergraduate seniors working to create a phase-lock loop for their senior project. The team is composed of seven members – Nicholas Bybee, Stuart Anderson, Jacob Atkinson, Reuben Morrell, Anthony Bailey, Mitch Crane and Anton Arriaga, all working under the supervision of professor Armin Tajalli [Link][Link].
Mead Course
March 25, 2020. Prof. Tajalli will present a short-course in Santa Cruz on: “Wireline SerDes Design,” as part of the Mead Courses (www.mead.ch).
IEEE SSCS Talk in ETHZ
June 18, 2019. Our IEEE SSCS (Switzerland Chapter at ETHZ) has been highlighted in the latest IEEE Solid-State Magazine (LINK). This talk was about the latest advancements in the field of wireline communications.
CICC’2020
January 16, 2020. Our paper entitled: “Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ” has been accepted for publication in IEEE ISCAS’2020. Congratulations to the team !
ISCAS’2020
January 5, 2020. Our paper entitled: “Power System Emulator Based on PLL Architecture” has been accepted for publication in IEEE ISCAS’2020. Congratulations to Asif Wahid and Sayed Abdullah Sadat !
JSSC’2020
January 4, 2020. Our paper entitled: “A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET” has been accepted for publication in IEEE JSSC. This article reports one of the lowest power high-speed links, that can be employed in applications such as High-Performance Computing and Machine Learning [Link].
Open Positions [closed]
August 14, 2019. New open positions are available: LCAS is hiring post-docs and PhD students. If you are interested in design of advanced analog circuit for high-speed communication systems, please do not hesitate sending us your CV [armin DOT tajalli AT utah DOT edu].
ISSCC’2019 Forum Presentation
February 21, 2019. The latest results of our research on Serial Communications will be presented in ISSCC (Forum 5: 56 Gb/s to 112 Gb/s and Beyond: Design Challenges and Solutions in Wireline Communications). The lecture is entitled: Non-Differential Techniques: Multi-Wire Multi-Level I/O [Link].
NEWCAS’2019 Paper
April 21, 2019. The works of Senior Project students working with LCAS has been accepted for publication in IEEE NEWCAS’2019 (Munich, Germany) ! The paper is entitled: CMOS Amplifier Design Based on Extended gm/ID Methodology. Congratulations to the team: Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchel Crane, Anthony Baily, and Reuben Morell. The team is proposing a very interesting and practical algorithm to design analog circuits based on an extended gm/Id methodology.
MWSCAS’2019 Paper
May 12, 2019. The works of Senior Project students working with LCAS has been accepted for publication in IEEE MWCAS’2019 (Dallas, US) ! The paper is entitled: Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. Congratulations to the team: Jacob Atkinson, Amin Aghighi, Stuart Anderson, Mitchel Crane, and Anthony Baily. This article is based on an extension to the earlier work of this group.