Books & Book Chapters:

  • A. Tajalli and Y. Leblebici, Extreme Low Power Mixed-Signal IC Design: Subthreshold Source-Coupled Circuits, Springer, 2010.
  • A. Tajalli and Y. Leblebici. Subthreshold Source-Coupled Logic, in Advanced Circuits for Emerging Technologies, 2012.
  • A. Tajalli, Network-in-Package for Low-Power and High-Performance, in Silicon Photonics for High-Performance Computing and Beyond, 57-68.
  • A. Aghighi, B. Farhang-Boroujeny, A. Tajalli, Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector, IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip.

Reports & Tutorials:

Dissertations:

  • Rajath Suparna Bindiganavile,  "Hybrid Pulse-Amplitude-Modulation Signaling Scheme and Clock Synthesis for Next Generation Ultra-High-Speed Wire-Line Transmitters," PhD Thesis Dissertation, University of Utah, May 2024 [Abstract_RB].
  • Asif Wahid,  "Hybrid Pulse-Amplitude-Modulation Signaling Scheme and Clock Synthesis for Next Generation Ultra-High-Speed Wire-Line Receivers," PhD Thesis Dissertation, University of Utah, May 2024 [Abstract_AW].

Selected Publications:

  • Michael Keyser, Farzad Ordubadi, and Armin Tajalli,  "Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators," IEEE MWSCAS, Springfield, MA, USA, 2024.
  • Rajath Bindiganavile, Asif Wahid, and Armin Tajalli,  "Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication," IEEE ISCAS, 2024.
  • Behdad Jamadi, and Armin Tajalli,  "Trade-Offs in Design of Wideband Inverter-Based Amplifiers," IEEE TVLSI, 2024.
  • Rajath Bindiganavile, Asif Wahid, and Armin Tajalli,  "Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication," IEEE ISCAS, 2024.
  • Armin Tajalli,  "Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using C/ID Methodology," IEEE LASCAS, 2024.
  • Rajath Bindiganavile, Asif Wahid, and Armin Tajalli,  "A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI," IEEE CICC, 2024.
  • Shea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, and Shiuh-hua Wood Chiang, "A 0.12-V 200-Hz-BW 10-bit ADC using quad-channel VCO and interpolation linearization," IEEE A-SSCC, 2023.
  • Shea Smith, Armin Tajalli, and Wood Chiang, "A VCO linearization technique using dual-VCO and interpolation for time-based ADCs," MWSCAS, 2023.
  • Sakthidasan Kalidasan, Armin Tajalli, "Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers," SMACD, 2023.
  • Behdad Jamadi, Farzad Ordubadi, Armin Tajalli, "Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology," SMACD, 2023.
  • A. Wahid, J. Atkinson, R. Bindiganavile, F. Jazaeri, and A. Tajalli, "Noise Aware Circuit Design Using C/ID-Invariant Algorithm," IEEE TCAS-II, July 2023.
  • Alec Adair and A. Tajalli, "Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study," IEEE ISCAS, August 2023.
  • J. Atkinson, A. Bailey, and A. Tajalli, "Systematic design of loop circuit topologies using C/IDS methodology," IEEE Trans VLSI, August 2022.
  • A. Tajalli and A. Shokrollahi, "Balanced circuit topologies and their application in data movement," IEEE MWSCAS August 2022.
  • R. Bindiganavile, A. Wahid, J. Atkinson, and A. Tajalli, "A 59-fs-rms 35-GHz PLL with FoM of -241-dB in 0.18-μm BiCMOS/SiGe Technology," IEEE RFIC July 2022.
  • R. Bindiganavile and A. Tajalli,"A Controlled KVCO Ring VCO Topology," IEEE MWSSCAS, August 2021.
  • A. Wahid and A. Tajalli,"Optimal PAM Order for Wireline Communications," IEEE ISCAS, May 2021.
  • A. Tajalli,"Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology," IEEE TCAS-I, Feb. 2021.
  • A. Tajalli, et al., "Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ," IEEE CICC, Boston 2020.
  • A. Tajalli, et al., "A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET," IEEE JSSC, 2020.
  • A. Wahid and A. Tajalli, "Digitally-Assisted Peak Detector for Periodic Signal," IEEE MWSCAS, 2020.
  • A. Wahid, S. A. Sadat, M. Ardakani, and A. Tajalli, "Power System Emulator Based on PLL Architecture," IEEE ISCAS, 2020.
  • A. Aghighi, B. Farhang-Boroujeni, and A. Tajalli, "Energy and Area Efficient Mixed-Mode MCMC MIMO Detector," IFIP/IEEE VLSI-SoC, 2020.
  • A. Aghighi, M. T. Azar, and A. Tajalli, "An ULP Self-Supplied Brain Interface Circuit," IFIP/IEEE VLSI-SoC, 2020.
  • A. Aghighi, A. Tajalli, and M. Taherzadeh, "A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors," IFIP/IEEE VLSI-SoC, 2020.," IFIP/IEEE VLSI-SoC, 2020.
  • Rajath Bindiganavile, Armin Tajalli, "Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling," IEEE MWSCAS 2019.
  • Jacob Atkinson, Amin Aghighi, Stuart Anderson, Anthony Bailey, Mitchell Crane, Armin Tajalli, "Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology," IEEE MWSCAS 2019.
  • A. Tajalli, “Matrix phase detector for high bandwidth and low jitter frequency synthesis,” IEE Electronics Letters, 2017.
  • G. Kim, C. Cao, K. Gharibdoust, S. A. Tajalli and Y. Leblebici, “A time-division multiplexing signaling scheme for inter-symbol/channel interference reduction in low-power multi-drop memory links,” TCAS-II, 2017.
  • A. Hormati, A. Tajalli, C. Walter, K. Gharibdoust and A. Shokrollahi, "A versatile spectrum shaping scheme for communicating beyond notches in multi-drop interfaces”. DesignCon, 2016.
  • K. Gharibdoust, A. Tajalli, and Y. Leblebici, “A 4x9-Gb/s 1-pJ/b hybrid NRZ/multi-tone I/O with crosstalk and ISI reduction for dense interconnect,” IEEE JSSC, 2016.
  • A. Shokrollahi, D. Carnelli, J. Fox, K. Hofstra, B. Holden, A. Hormati, P. Hunt, M. Johnston, J. Keay, S. Pesenti, R. Simpson, D. Stauffer, A. Stewart, G. Surace, A. Tajalli, O. Talebi Amiri, A. Tschank, R. Ulrich, C. Walter, F. Licciardello, Y. Mogentale, and A. Singh, “A pin efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5 coded SerDes up to 12mm for MCM packages in 28nm CMOS,” IEEE ISSCC, 2016.
  • K. Gharibdoust, A. Tajalli, and Y. Leblebici, “Hybrid NRZ/multi-tone serial data transceiver for multi-drop memory interfaces,” IEEE JSSC 2015.
  • M. Shoaran, A. Tajalli, M. Alioto, A. Schmid, and Y. Leblebici, “Aanalysis and characterisation of variability in subthreshold source-coupled logic circuits,” IEEE TCAS-I, 2015
  • K. Gharibdoust, A. Tajalli, and Y. Leblebici, “A 7.5mW 7.5Gb/s/lane mixed NRZ/muti-tone serial link transceive for multi-drop memory interfaces in 40nm CMOS,” IEEE ISSCC, 2015.
  • S. A. Tajalli and Y. Leblebici, "Wide-range dynamic power management in low-voltage low-power subthreshold SCL," IEEE TCAS-II, 2012.
  • A. Tajalli and Y. Leblebici, "Power and area efficient MOSFET-C filter for very low frequency applications," Springer Analog Integrated Circuits and Signal Processing, 2011.
  • A. Tajalli and Y. Leblebici, "Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter," IEEE TCAS-II, 2011.
  • A. Tajalli and Y. Leblebici, "Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS," IEEE TCAS-I, 2011.
  • A. Tajalli, M. Alioto and Y. Leblebici, "Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits," IEEE TCAS-II, 2009.
  • A. Tajalli and Y. Leblebici, “A slew controlled LVDS output driver circuit in 0.18um CMOS technology,” IEEE JSSC, 2009.
  • A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz, “Subthreshold source-coupled logic circuits for ultra low power applications,” IEEE JSSC, 2008.
  • A. Tajalli, P. Muller, and Y. Leblebici, “A power-efficient clock and data recovery circuit in 0.18-µm CMOS technology for multi-channel short-haul optical data communication,” IEEE JSSC, 2007.

Selected Patents:

  • A. Tajalli, A. Hormati, “Calibration apparatus and methods for sampler with adjustable high frequency gain,” US Patent Application, 2017.
  • A. Tajalli, “High performance phase locked loops,” US Patent Application, 2017.
  • A. Tajalli, "Voltage sampler driver with enhanced high frequency gain," US Patent Application, 2017.
  • A. Hormati, A. Shokrollahi, and A. Tajalli, "Vector signaling for densely routed wire groups," US Patent Application, 2017.
  • A. Tajalli, “Sampler with low input kickback,” US Patent Application, 2016.
  • A. Hormati, A. Tajalli, and A. Shokrollahi, “High speed communication system,” US Patent Application, 2015.
  • A. Tajalli, and M. Morin, “Narrow band receiver or transceiver,” US Patent Application, 2014.
  • A. Tajalli, “Symmetric linear equalizer circuit with enhanced gain,” US Patent, 2013.
  • A. Tajalli, "Automatic gain control with dual slope for amplifier," US Patent, 2012.
  • A. Tajalli, "Electronic circuit with unit to attenuating at least one input signal of amplifier," US Patent, 2012.
  • A. Tajalli, "Receiver systems," US Patent, 2012.
  • A. Tajalli, H. Cronie, and A. Shokrollahi, “Methods and circuits for effcient processing codes in serial data communication,” US Patent, 2011.
  • H. Cronie, A. Shokrollahi, and A. Tajalli, “Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes,” US Patent, 2011.